The International Linear Collider is a proposed e+e- collider designed for precision physics at the energy frontier. The SiD concept, one of the two designs for particle detectors being designed and developed, includes a Si-W electromagnetic tracking calorimeter [1]. It features a thin onion-skin construction of detection (silicon) and interaction (tungsten) layers, allowing for implementation of particle flow algorithms. The requirements of high granularity and thin readout layer are simultaneously met by employing 6 inch hexagonal silicon sensors, which are segmented into 13 mm2 pixels.

The requirements for high granularity are met by employing 6 inch hexagonal silicon sensors, which are segmented into 13 mm2 pixels. The sensors are read out by the KPiX chip, being developed at SLAC. The data readout bus consists of a hexagonally-stationed flexible kapton cable, which can handle up to sixteen KPiX chips. Currently, a version with a single station is used (shown in figure to left). Data transmission from the KPiX chip to the flex cable is accomplished via a set of short traces on the silicon sensor. Thus, the KPiX chip and the flex cable both need to be bonded to sets of pads on the silicon sensor. The bonding area on the flex cable, termed the “tongue.”

For the purposes of specifically testing solder ball bonding for the ILC KPiX project, two eutectic solders were selected for testing: a high temperature (melting point of 183 °C) eutectic lead/tin solder (Pb 63%, Sn 37%) for the KPiX bond and a low temperature solder (melting point of 143 °C) composed of indium/silver (In 97%, Ag 3%) for the flex cable.

The solder reflow process can be achieved in two ways: controlled gap and free-floating collapse. In the former, maintaining a minimum gap between the upper die and the lower wafer can ensure a perfectly coplanar bonding scenario. Since the placement arm contains a heater (in addition to the bottom heater in contact with the wafer) and always maintains contact with the KPiX chip, both items are also heated equally during reflow. An alternative to the controlled gap is free floating solder bonding, in which the upper arm releases the die such that it rests on the lower wafer. This technique can be difficult with nonuniform solder ball heights. Also, the KPiX chip is heated from only the bottom and the heat has to travel to the KPiX pads via the solder balls themselves. Any gap between solder and pad due to height difference prevents proper heating. An elongated heating time causes the solder to melt and allows its surface tension to pull the top chip into contact with more solder balls. At this point, the new physical contacts start heating their corresponding bonding pads and the attachment proceeds. However, it is greatly preferred to have pads at or near the temperature of the molten solder when contact is made. This may be achieved in a suitable reflow oven, but uniform heating of buried solder balls is a challenge due to the absence of convection. Hence, the preferred method for reflow is to use the controlled gap technique with uniform heating of the flip chip assembly.

To address the concern of heating the Si-W assembly through two different solder reflow steps, a series of tests were done using dummy chips. Two eutectic solders were selected for testing: a high temperature (melting point of 183 °C) eutectic lead/tin solder (Pb 63%, Sn 37%) for the KPiX bond and a low temperature solder (melting point of 143 °C) composed of indium/silver (In 97%, Ag 3%) for the flex cable. The KPiX chips manufactured by the Taiwan Semiconductor Manufacturing Company (TSMC) come with the high temperature eutectic solder balls already placed on the pads. For our studies, solder balls of the two types were placed on the dummy chips by CVInc. There was worry that a high temperature solder joint, bonded in the first stage of an attachment, would weaken and/or fail when brought near its melting temperature during the second stage. To determine the effect of this temperature cycling, a pair of dummy chips was bonded using high temperature solder (at 210 °C) and the resistances of the bond were measured. These values are shown in blue in figure 6, left, where each of the twenty measured pads is shown. The maximum resistance seen is 10 mΩ, which is acceptable for the application. The pair of bonded chips was then cycled up to 160 °C, which is the temperature that is used for bonding the low temperature solder. Afterward, the same 4-point resistances were measured. The yellow bars in figure 6 show the resistance of the sample after reheating. The resistances have all decreased to a range of 1-3 mΩ. This lowering may be explained as due to domain walls of nonuniform alloys in the solder shifting and decreasing electrical resistance. Clearly the resistances did not increase with the temperature cycle and thus this bonding scenario is acceptable. If placed on the silicon sensor, the low temperature solder will also be reflowed during the bonding of the KPiX chip, but with nothing attached.

Using dummy chips with low temperature solder, we first cycled the chip to a temperature of 210 °C to imitate the high temperature solder bond; the chip was not being bonded at this high temperature, but rather simply exposed to the high temperature. Following this high temperature exposure, the sample was cooled and then bonded to its mating dummy chip at the usual 160 °C. The figure above, shows the 4-point resistance measurements following this bonding process. Each of the twenty pads is within an acceptable range. The highest value of 24 mΩ does not cause concern as it is still much smaller than one ohm, which is our acceptance level.